1. Field
Example embodiments relate to a non-volatile memory device, and, for example, to a non-volatile memory device having a recess-type control gate electrode and methods of operating and fabricating the same.
2. Description of the Conventional Art
As semiconductor products' dimensions decrease and operation speeds increase, operation speed and integration of non-volatile memory devices used in these products has also increased. Accordingly, non-volatile memory devices having three-dimensional structures have replaced conventional art non-volatile memory devices having planar structures. Non-volatile memory devices having three-dimensional structures include, for example, recess-type control gate electrodes extended into semiconductor substrates.
Non-volatile memory devices having three-dimensional structures have channel areas larger than conventional art non-volatile memory devices with planar structures and, thus, have an increased operation current, which may result in increased speed of non-volatile memory devices.
However, non-volatile memory devices having three-dimensional structures may be limited as to how much their integration may increase, because they may still have large impurity doped areas such as source regions and drain regions. For example, non-volatile memory devices having NAND structures that are advantageous for integration may require larger, alternating source regions and drain regions, such that they may be limited as to how much their integration can increase.
FIG. 1 is a circuit diagram of a conventional art non-volatile memory device. In FIG. 1, word lines WLs and bit lines BLs may cross each other. Sources and drains (not shown) of memory transistors Tm may be connected to bit lines BLs. Control gates of memory transistors Tm may be connected to word lines WLs. Conventional art non-volatile memory devices having the above structure may be referred to as a nitride programmable read-only memory (NROM) device. Word lines WLs of an NROM device may have a larger impurity doped area, which may prevent or reduce integration of NROM devices.